The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also increased the complexity of processing and manufacturing ICs.
A lithography exposure process forms a patterned photoresist layer for various patterning processes, such as etching or ion implantation. In a typical lithography process, a photosensitive layer (resist) is applied to a surface of a semiconductor substrate, and an image of features defining parts of the semiconductor device is provided on the layer by exposing the layer to a pattern of light.
Advanced lithography processes have been developed to achieve smaller geometric sizes. For example, the use of extreme ultraviolet (EUV) lithography has been proposed to achieve small geometric sizes. Due to the heavy absorption of EUV radiation by certain substances, an EUV lithography system typically uses a reflective optics apparatus to carry out the lithography processes. However, conventional EUV lithography systems may suffer from the penumbra effect, which may lead to issues with device pattern uniformity or otherwise degrade lithographic performance.
Therefore, while existing lithography exposure apparatuses and processes have been generally adequate for their intended purposes, they are not entirely satisfactory in all respects.